The University of Massachusetts Microwave Remote Sensing Lab (MIRSL) is working with Stony Brook University/Brookhaven National Lab (SBU/BNL) to study atmospheric convection using Doppler radar. MIRSL is constructing a bistatic receiver to be used with the SBU/BNL Low-power Phased Array Radar (LPAR). The error in the system when a Global Positioning System Disciplined Oscillator (GPSDO) is used to synchronize the transmitter and receiver oscillator frequencies is examined.
Steven Beninati is a PhD student in the Microwave Remote Sensing Lab (MIRSL) at the University of Massachusetts Amherst. He received a B.S in Electrical Engineering from Rensselaer Polytechnic Institute. Steven’s research interests include remote sensing, instrumentation, and microwave systems
Drones (UAVs) are well-known for violating citizens’ privacy either inadvertently or deliberately. But they could be victims of privacy violations themselves in the sense that an adversary observing a UAV can infer its destination. We address the privacy protection problem in two major applications that require significantly different measures: (1) package delivery (2) Internet of Things (IoT) data collection. For each of these applications, we propose randomization mechanisms such that the adversary cannot simply identify the UAV's destination. We then analyze the privacy-utility trade-offs corresponding to each application.
Saeede Enayati is a 4th year PhD student in the Electrical & Computer Engineering department at University of Massachusetts, Amherst, under the advisory of Prof. Hossein Pishro-Nik. Her research interests include wireless communications and privacy.
We tuned the relaxation time of diffusive memristors and achieved uniform behavior. The dynamic relaxation behavior of such diffusive memristors is used as exponential decay kernels to implement the hierarchy of time surfaces algorithm. We designed a hierarchical circuit for the hardware implementation of HOTS, which showed a 77.3% accuracy in recognizing moving objects in the neuromorphic MNIST dataset according to our simulation. This work paves the way to low power neuromorphic hardware with integrated neuromorphic sensors and computing cores.
Yi Huang is a 4th-year Ph.D. student in the Electrical and Computer Engineering department at University of Massachusetts Amherst under the advisory of Prof. Qiangfei Xia. He earned his bachelor’s and master’s degree from Huazhong University of Science and Technology, Wuhan, China. His current research focuses on circuit and system designs based on emerging devices for energy-efficient neuromorphic computing.
6G is expected to provide global coverage by integrating terrestrial and non-terrestrial networks through network virtualization. Network slicing (NS) is a promising virtualization technique where the infrastructure is shared by multiple providers to serve multiple service classes. A multi-domain NS scheme that supports multiple configurations of satellite/airborne/terrestrial edge computing topologies is presented. Due to the varying dynamics in satellite-terrestrial networks, we develop an online adaptive slice selection and orchestration algorithm based on restless multi-armed bandits (RMABs), and we jointly optimize the slice configuration, service level agreement decomposition, routing, and resource allocation. Our scheme achieves 6 times higher reward than existing schemes.
Haitham Abdelhafez is a Ph.D. student in the Network Science Lab in the Electrical and Computer Engineering department at University of Massachusetts Amherst, USA under the supervision of Prof. Beatriz Lorenzo. His current research interest includes B5G and 6G mobile communication technologies. This includes the Device to Device (D2D) communications, the Internet of Things (IoT) communications, dynamic network slicing, satellite-terrestrial edge computing networks (STECNs) and AI-based applications in wireless communication systems.
General matrix multiplication (GEMM) is common to many applications. Due to its widespread use, a new generation of processors called Tile Matrix Multiply Unit (TMUL) features GEMM acceleration in hardware. Recent findings of Silent Data Corruptions (SDCs) in GEMM at data centers were reported. Algorithm-Based Fault Tolerance (ABFT) is an efficient mechanism for detecting and correcting errors in GEMM, but classic ABFT solutions are not optimized for hardware acceleration. We implemented a novel ABFT implementation directly on hardware. We propose two different TMUL architectures representing two design points and illustrate how ABFT can be directly incorporated into the TMUL hardware.
Sandeep Bal is a 2nd year Ph.D. student in the Electrical and Computer Engineering department at the University of Massachusetts Amherst. He completed his bachelors in Electronics and Communications Engineering from Maulana Abul Kalam Azad University (previously known as West Bengal University of Technology), India. His research interests currently lie in the intersection of deep learning hardware, reliability and sparsity management in machine learning. In his free time, he loves playing and watching football and practice strength training. He is also an ardent Cristiano Ronaldo and Real Madrid fan. Hala Madrid!
With increasingly deployed cameras and the rapid advances of Computer Vision, large-scale live video analytics becomes feasible. However, analyzing videos is compute-intensive. In addition, live video analytics needs to be performed in real time. We propose to perform configuration adaptation without profiling video online. We select configurations with a prediction model based on object movement features. We evaluate our system with two video analytic applications, road traffic monitoring and pose detection. The experimental results show that our profiling-free adaptation reduces the workload by 80\% of the state-of-the-art adaptation and increases the accuracy by 2-8%.
Tian Zhou is a Ph.D. candidate in the Department of Electrical and Computer Engineering, University of Massachusetts Amherst, under the advisory of Prof. Lixin Gao. His research interests includes machine learning, cloud computation, distributed system, and information privacy and security.
Deep Neural Networks (DNNs) have become ubiquitous in real world deployments. However, they face a variety of threats as their usage spreads. Model extraction attacks, which steal DNN models, endanger intellectual property, data privacy, and security. To mitigate these risks, AI providers want to proactively discover vulnerabilities enabling model extraction attacks. In this work, we propose a novel, simple, and effective DNN architecture extraction attack which uses aggregate rather than time-series GPU profiles as a side-channel to predict DNN architecture. Our attack achieves state-of-the-art performance, correctly predicting the entire set of PyTorch vision architectures with 100% accuracy.
Jonah O’Brien Weiss is a second year master’s student in computer engineering advised by Professor Kundu. He received his bachelor’s degree in the same field from UMass in 2021. His research focuses on the security of deployed deep learning models by investigating algorithmic and implementation-specific vulnerabilities. In the past, Jonah has worked on securing hardware components across Dell’s supply chain, tested the reliability of Tesla’s home battery system, and built a warehouse-cleaning robot for Amazon Robotics. Outside of work, he enjoys playing and watching soccer and playing the drums.
The Federated Learning (FL) technique builds machine learning models on distributed edge-devices without exposing their private data. However, FL may is liable to fairness issues due to data diversity across devices. We propose and implement Global FL to produce fair FL models that preserve the group fairness and global individual fairness property.
Khotso Selialia is a 2nd year PhD student in the Electrical and Computer Engineering department at the university of Massachusetts Amherst, where he is advised by Prof. Fatima Anwar. His research focuses on eliminating performance bias in distributed learning for emerging embedded technologies.
A formal verification method for hardware implementation of restoring divider circuits is presented. This method is based on setting selected signals to predefined constants to reduce the design to easily verifiable circuit components, followed by their verification using equivalence checking and SAT. In contrast to previous approaches, the verification is done on a functional level without any reverse engineering of the internal structure. This method facilitates debugging by localizing the source of a bug, a feature not currently available from the existing verification tools. The results show significant improvement in verification time compared to other methods.
Jiteshri Dasari is a 2nd year PhD student in the VLSI CAD lab under the supervision of Prof. Maciej Ciesielski. Her research interests are in formal verification of arithmetic circuits. Through her research, she aims to tackle the compute and memory intensive issues in the formal verification of complex datapath circuits. Prior to starting her PhD journey, she worked for about 3 years in the VLSI design industry. In her spare time, she loves traveling and sketching.
The objectives of this study were to test the feasibility of the developed waterproof wearable device with Surface Electromyography (sEMG) sensor and Inertial Measurement Unit (IMU) sensor by Comparing the onset duration of sEMG recordings from maximal voluntary contractions (MVC), Comparing the acceleration of arm movement from IMU, and Observing the reproducibility of onset duration and acceleration from the developed device for bicep brachii (BB) muscle between on dry-land, and in aquatic environments.
Abu Bony Amin is a PhD student in the Department of Electrical and Computer Engineering (ECE) at the University of Massachusetts Amherst, joined in Fall 2021. Previously, he studied MS in Electrical Engineering at Florida Polytechnic University in Lakeland, FL, completing his BS in Electrical and Electronic Engineering (EEE) from the Chittagong University of Engineering and Technology (CUET) in Chittagong, Bangladesh. His Master's thesis was about developing configuration of CNT bundles to improve the performance of CNT based VLSI interconnect. His current research interest focuses on hardware design and firmware programming for biometric devices and circuits.
The excitation-contraction dynamics in cardiac tissue are the most important physiological parameters for assessing developmental state. We demonstrate integrated nanoelectronic sensors capable of simultaneously probing electrical and mechanical cellular responses. The sensor is configured from a three-dimensional nanotransistor with its conduction channel protruding out of the plane. The structure promotes not only a tight seal with the cell for detecting action potential via field effect but also a close mechanical coupling for detecting cellular force via piezoresistive effect. Arrays of nanotransistors are integrated to realize label-free, submillisecond, and scalable interrogation of correlated cell dynamics, showing advantages in tracking and differentiating cell states in drug studies. The sensor can further decode vector information in cellular motion beyond typical scalar information acquired at the tissue level, hence offering an improved tool for cell mechanics studies. The sensor enables not only improved bioelectronic detections but also reduced invasiveness through the two-in-one converging integration.
One fundamental classification method of supervised learning is support vector machine. In this poster, we consider the setting of hypothesis attack on a binary classification task. For simplicity, we assume there exists two possible attributes of one client's training data points. An adversary infers the true attribute based on the exposed gradients. Hypothesis testing is employed by the adversary. Specifically, total variation distance is applied to calculate the optimal probability of error and model the privacy constraint. In addition, transition matrix is used for obfuscation to protect privacy. Finally, the privacy and utility trade-off is modeled by an optimization problem.
Bo Guan received the B.Eng. degree in Electrical Engineering from Northeastern University, and the M.Sc. degree in Electrical Engineering from Northwestern University, in 2015 and 2017, respectively. He is currently pursuing the Ph.D. degree with the Department of Electrical and Computer Engineering, University of Massachusetts Amherst. His current research studies focus on information privacy and security.
Performance analysis is challenging as the performance issue of a complex system can be originated from any component inside the whole software stack. However, few existing tools could help users understand the performance bottleneck inside the complex system stack. To bridge this gap, we propose a novel analysis method–“Cross Flow Analysis (CFA)”– that monitors the interactions/flows across components, such as between the application and libraries, or between different libraries. On top of XFA, we built the Scaler profiler. Scaler proposes multiple new techniques, called lightweight PLT interposition, online data folding, and multithreaded runtime attribution. These techniques enable Scaler to simultaneously achieve low runtime overhead, low memory overhead, and high profiling accuracy. Experiment results show that Scaler can detect multiple unknown performance issues while other profilers cannot.
Steven is a second year PhD candidate advised by Prof. Tongping Liu. His research interest is software system performance profiling and optimization. He is enthusiastic about exploring the frontiers of software technology and building useful tools and products for users. Check steven's website at https://www.xttechgroup.com
Here we present the design and assembly of a room-temperature ion trap system which allows for rapid prototyping of novel trap designs, such that each new chip can be installed and reach UHV in under 2 days. We achieve this by fabricating our own custom surface Paul traps in the UMass Amherst cleanroom facilities, which are then argon ion milled, diced, mounted and wire bonded to an interposer which is placed in an ultra-high vacuum chamber and baked in a conventional oven for about 46 hours. Thus far, we have demonstrated the system’s ability to maintain chains of up to 6 strontium ions. Future work will see the system being used to study the effect of various trap geometries, process fabrication steps and surface treatments on anomalous heating rates and for portable quantum sensing applications, as an optical atomic clock.
Chris is a research assistant in Professor Niffenegger's Trapped Ion and Photonics laboratory. He received a B.S. in electrical engineering and physics from UMass Amherst and is now a second-year Master's student in ECE. As an undergraduate, he was a staff member at the UMass Amherst M5 makerspace, and has served as a graduate TA for the senior design project capstone course in ECE. He plans to continue his work in trapped ion quantum computing next year as a PhD candidate in the UMass Physics program. Outside of the lab, Chris enjoys baking bread, playing board games, and making coffee.