Daniel Holcomb
Associate Professor
Electrical and Computer Engineering
University of Massachusetts Amherst
My research is on building secure embedded systems that are also reliable and efficient. I lead a laboratory of talented researchers that pursue these goals working broadly across computer engineering topics such as formal verification, CAD, and VLSI design. Current projects are on designing secure hardware (low-power ASIC and FPGA), obfuscation and reverse engineering, interdomain routing, and supply chain security.
A Deric, D Holcomb "Know Time to Die – Integrity Checking for Zero Trust Chiplet-based Systems Using Between-Die Delay PUFs", CHES 2022
[Paper] |
X Li, R Tessier, D Holcomb, "Precise Fault Injection to Enable DFIA
for Attacking AES in Remote FPGAs, FCCM 2022
[Paper] |
S N Dhanuskodi, X Li, D Holcomb "COUNTERFOIL: Verifying Provenance of Integrated Circuits using Intrinsic Package Fingerprints and Inexpensive Cameras", USENIX security 2020
[Paper] [Software/Data] |
S N Dhanuskodi, S Allen, D Holcomb, "Efficient Register Renaming Architectures for 8-bit AES Datapath at 0.55pJ/bit in 16nm FinFET", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020. |
G Provelengios, D Holcomb, R Tessier "Characterizing Power Distribution Attacks in Multi-User FPGA Environments", International Conference on Field-Programmable Logic and Applications (FPL), 1-8, 2019. Winner of Stamatis Vassiliadis Best Paper Award
[Paper] |
S N Dhanuskodi, D Holcomb "Enabling Microarchitectural Randomization in Serialized AES Implementations to Mitigate Side Channel Susceptibility", IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2019. Winner of Best Poster Award |
G Provelengios, C Ramesh, S B Patil, K Eguro, R Tessier, D Holcomb "Characterization of Long Wire Data Leakage in Deep Submicron FPGAs", International Symposium on Field-Programmable Gate Arrays, 292-297, 2019. |
N Dumpala, S B Patil, D Holcomb, R Tessier "Loop Unrolling for Energy Efficiency in Low-Cost Field-Programmable Gate Arrays", ACM Transactions on Reconfigurable Technology and Systems (TRETS) 11 (4), 26, 2019. |
H Jiang, C Li, R Zhang, P Yan, P Lin, Y Li, JJ Yang, D Holcomb, Q Xia "A provable key destruction scheme based on memristive crossbar arrays", Nature Electronics 1 (10), 2018. |
M Usmani, S Keshavarz, E Matthews, L Shannon, R Tessier, D Holcomb, "Efficient PUF-Based Key Generation in FPGAs using Per-Device Configuration", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27 (2), 364-375, 2018. |
S Keshavarz, C Yu, S Ghandali, X Xu, D Holcomb "Survey on Applications of Formal Methods in Reverse Engineering and Intellectual Property Protection", Journal of Hardware and Systems Security 2 (3), 214-224, 2018. |
X Xu, S Keshavarz, D Forte, M Tehranipoor, D Holcomb "Bimodal Oscillation as a Mechanism for Autonomous Majority Voting in PUFs", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26 (11), 2431-2442. 2018 |
C Ramesh, SB Patil, SN Dhanuskodi, G Provelengios, S Pillement, D Holcomb, R Tessier "FPGA Side Channel Attacks without Physical Access", 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 45-52, 2018.
[Paper] |
S Keshavarz, F Schellenberg, B Richter, C Paar, D Holcomb "SAT-based Reverse Engineering of Gate-Level Schematics using Fault Injection and Probing",
IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 215-220, 2018. Winner of Best Poster Award
[Paper] |
A Shanmugam, M Usmani, A Mayberry, DL Perkins, DE Holcomb "Imaging systems and algorithms to analyze biological samples in real-time using mobile phone microscopy", PloS one, 2018. |
R Zhang, H Jiang, Z Wang, P Lin, Y Zhuo, D Holcomb, D Zhang, JJ Yang, Q Xia "Nanoscale Diffusive Memristor Crossbars as Physical Unclonable Functions", Nanoscale, 2018. |
S Keshavarz, D Holcomb "Threshold-based obfuscated keys with quantifiable security against invasive readout", 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017.
[Paper] |
SN Dhanuskodi, D Holcomb "An improved clocking methodology for energy efficient low area AES architectures using register renaming", IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED'17), 2017.
[Paper] |
SN Dhanuskodi, D Holcomb "Techniques to reduce switching and leakage energy in unrolled block ciphers", IEEE Transactions on Computers, 2017. |
D Holcomb "Nanoscale CMOS Memory-based Security Primitive Design", Security Opportunities in Nano Devices and Emerging Technologies, M. Tehranipoor, D. Forte, G. Rose, S. Bhunia (Eds.), Publisher: CRC Press/Taylor & Francis, 2017. |
V C Patil, A Vijayakumar, D E Holcomb, S Kundu "Improving reliability of weak PUFs via circuit techniques to enhance mismatch", International Symposium on Hardware Oriented Security and Trust (HOST), 146-150, 2017. |
N K Dumpala, S B Patil, D Holcomb, R Tessier "Energy efficient loop unrolling for low-cost FPGAs", IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 117-120, 2017. |
S Keshavarz, D Holcomb "Privacy Leakages in Approximate Computation", IEEE International Symposium on Circuits and Systems (ISCAS'17), 2017. |
S Keshavarz, C Paar, D Holcomb "Design automation for obfuscated circuits with multiple viable functions", In Proceedings of Design Automation and Test in Europe (DATE '17)., March, 2017.
[Paper] |
C Yu, D Holcomb, M Ciesielski "Reverse engineering of irreducible polynomials in GF (2 m) arithmetic", In Proceedings of Design Automation and Test in Europe (DATE '17)., March, 2017.
[Paper] |
C Yu, X Zhang, D Liu, M Ciesielski, D Holcomb "Incremental SAT-based Reverse Engineering of Camouflaged Logic Circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, January, 2017.
[Software] |
X Xu, DE Holcomb "Reliable PUF design using failure patterns from time-controlled power gating", Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2016. |
X Xu, DE Holcomb "A clockless sequential PUF with autonomous majority voting", Great Lakes Symposium on VLSI, 2016. |
SN Dhanuskodi, D Holcomb "Energy Optimization of Unrolled Block Ciphers using Combinational Checkpointing", RFIDSec 2016: 12th Workshop on RFID and IoT Security, 2016. |
A Vijayakumar, VC Patil, DE Holcomb, C Paar, S Kundu "Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device-and Logic-Level Techniques", IEEE Transactions on Information Forensics and Security, 2016. |
S Ghandali, GT Becker, D Holcomb, C Paar "A Design Methodology for Stealthy Parametric Trojans and Its Application to Bug Attacks", Cryptographic Hardware and Embedded Systems (CHES'16), 2016.
[Paper] |
SN Dhanuskodi, S Keshavarz, D Holcomb "LLPA: Logic State Based Leakage Power Analysis", 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016. |
X Xu, W Burleson, DE Holcomb "Using Statistical Models to Improve the Reliability of Delay-Based PUFs", VLSI (ISVLSI), 2016 IEEE Computer Society Annual Symposium on, 2016. |
S Vyas, NK Dumpala, R Tessier, DE Holcomb "Improving the Efficiency of PUF-Based Key Generation in FPGAs using Variation-Aware Placement", 26th International Conference on Field-Programmable Logic and Applications (FPL), 2016. |
J Hester, N Tobias, A Rahmati, L Sitanayah, DE Holcomb, K Fu, W Burleson, J Sorber "Persistent Clocks for Batteryless Sensing Devices", ACM Transactions on Embedded Computing Systems (TECS), 2016. |
Liu D, Yu C, Zhang X, and Holcomb DE "Oracle-Guided Incremental SAT Solving to Reverse Engineer Camouflaged Logic Circuits", In Proceedings of Design Automation and Test in Europe (DATE '16)., March, 2016.
[Paper] |
Rahmati A, Hicks M, Holcomb DE, and Fu K, "Probable Cause: The Deanonymizing Effects of Approximate DRAM", in ISCA'15: Proceedings of the 42nd Annual International Symposium on Computer Architecture, June 2015. |
Xu X, Rührmair U, Holcomb DE, and Burleson WP, "Security Evaluation and Enhancement of Bistable Ring PUFs", In RFIDSec'15: Proceedings of the 11th international conference on Radio Frequency Identification: security and privacy issues., June, 2015.
[Paper] |
Xu X, Rahmati A, Holcomb DE, Fu K and Burleson W, "Reliable Physical Unclonable Functions using Data Retention Voltage of SRAM Cells", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, June 2015, Vol. 34(6), pp. 903-914. |
Holcomb DE and Fu K, "Bitline PUF: Building Native Challenge-Response PUF Capability into Any SRAM", In Cryptographic Hardware and Embedded Systems (CHES 2014)., September, 2014. Vol. 8731, pp. 510-526. |
Rührmair U and Holcomb DE, "PUFs at a Glance", In Proceedings of Design Automation and Test in Europe (DATE '14)., March, 2014. |
Holcomb DE and Seshia SA, "Compositional Performance Verification of Network-on-Chip Designs", Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. Vol. 33(9), pp. 1370-1383. |
Holcomb DE and Fu K, "QBF-Based Synthesis of Optimal Word-Splitting in Approximate Multi-Level Storage Cells", In Workshop on Approximate Computing Across the System Stack (WACAS). Salt Lake City, UT, March, 2014. |
Rahmati A, Hicks M, Holcomb DE and Fu K, "Refreshing Thoughts on DRAM: Power Saving vs. Data Integrity", In Workshop on Approximate Computing Across the System Stack (WACAS). Salt Lake City, UT, March, 2014.
[Paper] |
Jha S, Talalay M, Holcomb D, Ogras U, Kishinevsky M, Klinglesmith M, De Gruijl R and Choi S, "Automated Design Space Exploration for SoC Interconnects", Intel Design Technology and Tools Conference. |
Holcomb DE, Gotmanov A, Kishinevsky M and Seshia SA, "Compositional Performance Verification of NoC Designs", In Proceedings of the 10th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE)., July, 2012. , pp. 1-10. |
Holcomb DE, Rahmati A, Salajegheh M, Burleson WP and Fu K, "DRV-Fingerprinting: using data retention voltage of SRAM cells for chip identification", In RFIDSec'12: Proceedings of the 8th international conference on Radio Frequency Identification: security and privacy issues., July, 2012. Springer-Verlag.
[Paper] |
Rahmati A, Salajegheh M, Holcomb D, Sorber J, Burleson WP and Fu K, "TARDIS: Time and Remanence Decay in SRAM to Implement Secure Protocols on Embedded Devices without Clocks", In Proceedings of the 21st USENIX Security Symposium. Bellevue, WA, August, 2012.
[Paper] |
Brady BA, Holcomb D and Seshia SA, "Counterexample-guided smt-driven optimal buffer sizing", In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011. , pp. 1-6. |
Holcomb D, Brady B and Seshia S, "Abstraction-based performance verification of NoCs", In Proceedings of the 48th Design Automation Conference., June, 2011. , pp. 492-497. |
Lin L, Holcomb DE, Krishnappa DK, Shabadi P and Burleson W, "Low-power sub-threshold design of secure physical unclonable functions", Low-Power Electronics and Design (ISLPED), 2010 ACM/IEEE International Symposium on. , pp. 43-48. |
Zaveri RA, Voss PB, Berkowitz CM, Fortner E, Zheng J, Zhang R, Valente RJ, Tanner RL, Holcomb D, Hartley TP and Baran L, "Overnight atmospheric transport and chemical processing of photochemically aged Houston urban and petrochemical industrial plume", Journal of Geophysical Research: Atmospheres (1984--2012). Vol. 115(D23) Wiley Online Library. |
Holcomb DE, Burleson WP and Fu K, "Power-up SRAM State as an Identifying Fingerprint and Source of True Random Numbers", IEEE Transactions on Computers., September, 2009. Vol. 58(9), pp. 1198-1210.
[Paper] |
Holcomb DE, Li W and Seshia SA, "Design as you see FIT: System-level soft error analysis of sequential circuits", In Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09. , pp. 785-790.
[Paper] [Software] [User Guide] |
Holcomb DE, Burleson WP and Fu K, "Initial SRAM State as a Fingerprint and Source of True Random Numbers for RFID Tags", In Proceedings of the Conference on RFID Security., July, 2007.
[Paper] |
Riddle EE, Voss PB, Stohl A and Holcomb DE, "Trajectory model validation using newly developed altitude-controlled balloons during the International Consortium for Atmospheric Research on Transport and Transformations 2004 campaign", Journal of Geophysical Research. |
FPGA voltage during power attack
2018 Testchip
SAT formulation of fault injection